Commit 9a2e27e2 authored by Jason Yu's avatar Jason Yu Committed by Henrik Brix Andersen
Browse files

drivers: hwinfo: mcux_src_rev2: Change it to native driver 



The reset source is SOC specific, MCUX SDK SRC driver is
also SOC specific, it doesn't mask the SOC differences.
So the driver can use SOC macros directly, and handle SOC
differences in the hwinfo driver, not necessary to wrap
MCUX SDK driver.

Signed-off-by: default avatarJason Yu <zejiang.yu@nxp.com>
parent bd10f930

drivers/hwinfo/hwinfo_mcux_src_rev2.c

+22 −25
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2022 NXP

 * Copyright (c) 2022, 2025 NXP

 *

 * SPDX-License-Identifier: Apache-2.0

 */
@@ -10,30 +10,27 @@ 
#include <zephyr/drivers/hwinfo.h>

#include <string.h>

#include <zephyr/sys/byteorder.h>

#include <fsl_soc_src.h>



#ifdef CONFIG_CPU_CORTEX_M7

#define MCUX_RESET_PIN_FLAG kSRC_M7CoreIppUserResetFlag

#define MCUX_RESET_SOFTWARE_FLAG kSRC_M7CoreM7LockUpResetFlag

#define MCUX_RESET_POR_FLAG kSRC_M7CoreIppResetFlag

#define MCUX_RESET_WATCHDOG_FLAG (kSRC_M7CoreWdogResetFlag |			\

				kSRC_M7CoreWdog3ResetFlag |			\

				kSRC_M7CoreWdog4ResetFlag)

#define MCUX_RESET_DEBUG_FLAG kSRC_M7CoreJtagResetFlag

#define MCUX_RESET_SECURITY_FLAG kSRC_M7CoreCSUResetFlag

#define MCUX_RESET_TEMPERATURE_FLAG kSRC_M7CoreTempsenseResetFlag

#define MCUX_RESET_USER_FLAG kSRC_M7CoreM7RequestResetFlag

#define MCUX_RESET_PIN_FLAG      SRC_SRSR_IPP_USER_RESET_B_M7_MASK

#define MCUX_RESET_SOFTWARE_FLAG SRC_SRSR_M7_LOCKUP_M7_MASK

#define MCUX_RESET_POR_FLAG      SRC_SRSR_IPP_RESET_B_M7_MASK

#define MCUX_RESET_WATCHDOG_FLAG                                                                   \

	(SRC_SRSR_WDOG_RST_B_M7_MASK | SRC_SRSR_WDOG3_RST_B_M7_MASK | SRC_SRSR_WDOG4_RST_B_M7_MASK)

#define MCUX_RESET_DEBUG_FLAG       SRC_SRSR_JTAG_RST_B_M7_MASK

#define MCUX_RESET_SECURITY_FLAG    SRC_SRSR_CSU_RESET_B_M7_MASK

#define MCUX_RESET_TEMPERATURE_FLAG SRC_SRSR_TEMPSENSE_RST_B_M7_MASK

#define MCUX_RESET_USER_FLAG        SRC_SRSR_M7_REQUEST_M7_MASK

#elif defined(CONFIG_CPU_CORTEX_M4)

#define MCUX_RESET_PIN_FLAG kSRC_M4CoreIppUserResetFlag

#define MCUX_RESET_SOFTWARE_FLAG kSRC_M4CoreM7LockUpResetFlag

#define MCUX_RESET_POR_FLAG kSRC_M4CoreIppResetFlag

#define MCUX_RESET_WATCHDOG_FLAG (kSRC_M4CoreWdogResetFlag |			\

				kSRC_M4CoreWdog3ResetFlag |			\

				kSRC_M4CoreWdog4ResetFlag)

#define MCUX_RESET_DEBUG_FLAG kSRC_M4CoreJtagResetFlag

#define MCUX_RESET_SECURITY_FLAG kSRC_M4CoreCSUResetFlag

#define MCUX_RESET_TEMPERATURE_FLAG kSRC_M4CoreTempsenseResetFlag

#define MCUX_RESET_USER_FLAG kSRC_M4CoreM7RequestResetFlag

#define MCUX_RESET_PIN_FLAG      SRC_SRSR_IPP_USER_RESET_B_M4_MASK

#define MCUX_RESET_SOFTWARE_FLAG SRC_SRSR_M7_LOCKUP_M4_MASK

#define MCUX_RESET_POR_FLAG      SRC_SRSR_IPP_RESET_B_M4_MASK

#define MCUX_RESET_WATCHDOG_FLAG                                                                   \

	(SRC_SRSR_WDOG_RST_B_M4_MASK | SRC_SRSR_WDOG3_RST_B_M4_MASK | SRC_SRSR_WDOG4_RST_B_M4_MASK)

#define MCUX_RESET_DEBUG_FLAG       SRC_SRSR_JTAG_RST_B_M4_MASK

#define MCUX_RESET_SECURITY_FLAG    SRC_SRSR_CSU_RESET_B_M4_MASK

#define MCUX_RESET_TEMPERATURE_FLAG SRC_SRSR_TEMPSENSE_RST_B_M4_MASK

#define MCUX_RESET_USER_FLAG        SRC_SRSR_M7_REQUEST_M4_MASK

#else

/* The SOCs currently supported have an M7 or M4 core */

#error "MCUX SRC driver not supported for this CPU!"
@@ -44,7 +41,7 @@ BUILD_ASSERT(DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) == 1, "No nxp,imx-src compat 
int z_impl_hwinfo_get_reset_cause(uint32_t *cause)

{

	uint32_t flags = 0;

	uint32_t reason = SRC_GetResetStatusFlags((SRC_Type *)DT_INST_REG_ADDR(0));

	uint32_t reason = ((SRC_Type *)DT_INST_REG_ADDR(0))->SRSR;



	if (reason & (MCUX_RESET_PIN_FLAG)) {

		flags |= RESET_PIN;
@@ -78,9 +75,9 @@ int z_impl_hwinfo_get_reset_cause(uint32_t *cause) 


int z_impl_hwinfo_clear_reset_cause(void)

{

	uint32_t reason = SRC_GetResetStatusFlags((SRC_Type *)DT_INST_REG_ADDR(0));

	uint32_t reason = ((SRC_Type *)DT_INST_REG_ADDR(0))->SRSR;



	SRC_ClearGlobalSystemResetStatus((SRC_Type *)DT_INST_REG_ADDR(0), reason);

	((SRC_Type *)DT_INST_REG_ADDR(0))->SRSR = reason;



	return 0;

}

modules/hal_nxp/mcux/mcux-sdk-ng/drivers/drivers.cmake

+0 −1
Original line number Diff line number Diff line
@@ -12,7 +12,6 @@ elseif(CONFIG_ARCH STREQUAL "arm") 
  zephyr_library_sources(${MCUX_SDK_NG_DIR}/drivers/common/fsl_common_arm.c)

endif()



set_variable_ifdef(CONFIG_HWINFO_MCUX_SRC_V2    CONFIG_MCUX_COMPONENT_driver.src_2)

set_variable_ifdef(CONFIG_GPIO_MCUX_IGPIO       CONFIG_MCUX_COMPONENT_driver.igpio)

set_variable_ifdef(CONFIG_ADC_MCUX_LPADC        CONFIG_MCUX_COMPONENT_driver.lpadc)

set_variable_ifdef(CONFIG_COUNTER_MCUX_CTIMER   CONFIG_MCUX_COMPONENT_driver.ctimer)

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