arch: arm: cortex_a_r: Set VBAR for all cores

What is changed?
Secondary cores can now boot successfully on cache and non-cache
coherent systems if the Zephyr image/vector table is loaded at an
address other than the default address 0x0.

How is it changed?
1. By calling the relocate_vector() from reset.S as part of EL1 reset
   initialization instead of prep_c to have VBAR set for all cores and
   not just for the primary core.
2. Remove dead code under CONFIG_SW_VECTOR_RELAY and
   CONFIG_SW_VECTOR_RELAY_CLIENT.

Why do we need this change?
1. As reported in issue #76182, on Cortex_ar, VBAR is set only for
   the primary cores while VBAR for the secondary cores are left with
   default value 0.
   This results in Zephyr not booting on secondary cores if the vector
   table for secondary cores is loaded at an address other than 0x0.
   VBAR is set in relocate_vector() so we move it to reboot.c which is
   better suited to have configs related to system control block.
2. The two SW_VECTOR_RELAY configs have a direct dependency on
   CONFIG_CPU_CORTEX_M, which is disabled while compiling for
   Cortex-A and Cortex-R hence leading to a dead code.

How is the change verified?
Verified with fvp_baser_aemv8r/fvp_aemv8r_aarch32/smp.

Signed-off-by: Sudan Landge <sudan.landge@arm.com>