Commit ac174d30 authored by Daniel DeGrasse's avatar Daniel DeGrasse Committed by Carles Cufi
Browse files

boards: mimxrt1015_evk: Enable ADC on RT1015



Enables ADC on RT1015 evaluation board. Channels 1 and 13 are exposed as
pins 2 and 1 of J18 on the EVK.

Signed-off-by: default avatarDaniel DeGrasse <daniel.degrasse@nxp.com>
parent 4e6ac932
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+6 −0
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@@ -76,6 +76,8 @@ features:
+-----------+------------+-------------------------------------+
| USB       | on-chip    | USB device                          |
+-----------+------------+-------------------------------------+
| ADC       | on-chip    | ADC                                 |
+-----------+------------+-------------------------------------+

The default configuration can be found in the defconfig file:
``boards/arm/mimxrt1015_evk/mimxrt1015_evk_defconfig``
@@ -114,6 +116,10 @@ The MIMXRT1015 SoC has five pairs of pinmux/gpio controllers.
+---------------+-----------------+---------------------------+
| GPIO_AD_B0_13 | LPSPI1_SDI      | SPI                       |
+---------------+-----------------+---------------------------+
| GPIO_AD_B0_14 | ADC             | ADC1 Channel 1            |
+---------------+-----------------+---------------------------+
| GPIO_AD_B1_13 | ADC             | ADC1 Channel 13           |
+---------------+-----------------+---------------------------+

System Clock
============
+4 −0
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@@ -101,3 +101,7 @@ arduino_serial: &lpuart4 {};
zephyr_udc0: &usb1 {
	status = "okay";
};

&adc1 {
	status = "okay";
};
+1 −0
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@@ -22,3 +22,4 @@ supported:
  - i2c
  - usb_device
  - spi
  - adc
+13 −0
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@@ -106,6 +106,19 @@ static int mimxrt1015_evk_init(const struct device *dev)
			IOMUXC_SW_PAD_CTL_PAD_DSE(6));
#endif

#if DT_NODE_HAS_STATUS(DT_NODELABEL(adc1), okay) & CONFIG_ADC
	/* ADC1 Channels 1 and 13 exposed as pins 2 and 1 on J18 of eval board */
	IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_14_GPIO1_IO14, 0U);
	IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_13_GPIO1_IO29, 0U);

	IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_14_GPIO1_IO14,
				IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
				IOMUXC_SW_PAD_CTL_PAD_DSE(6));
	IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_13_GPIO1_IO29,
				IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
				IOMUXC_SW_PAD_CTL_PAD_DSE(6));
#endif

	return 0;
}

+12 −0
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/*
 * SPDX-License-Identifier: Apache-2.0
 *
 * Copyright (c) 2021 NXP
 */

/ {
	zephyr,user {
		/* adjust channel number according to pinmux in board.dts */
		io-channels = <&adc1 13>;
	};
};
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