Commit 4e6ac932 authored by Daniel DeGrasse's avatar Daniel DeGrasse Committed by Carles Cufi
Browse files

boards: mimxrt1010_evk: Added ADC support to RT1010



Added ADC support to RT1010 evaluation board. ADC channels 1 and 2 are
exposed as pins 10 and 12 of J26.

Signed-off-by: default avatarDaniel DeGrasse <daniel.degrasse@nxp.com>
parent b0d613d9
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+6 −0
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@@ -76,6 +76,8 @@ features:
+-----------+------------+-------------------------------------+
| USB       | on-chip    | USB device                          |
+-----------+------------+-------------------------------------+
| ADC       | on-chip    | adc                                 |
+-----------+------------+-------------------------------------+

The default configuration can be found in the defconfig file:
``boards/arm/mimxrt1010_evk/mimxrt1010_evk_defconfig``
@@ -110,6 +112,10 @@ The MIMXRT1010 SoC has five pairs of pinmux/gpio controllers.
+---------------+-----------------+---------------------------+
| GPIO_AD_06    | LPSPI1_SCK      | SPI                       |
+---------------+-----------------+---------------------------+
| GPIO_AD_01    | ADC             | ADC1 Channel 1            |
+---------------+-----------------+---------------------------+
| GPIO_AD_02    | ADC             | ADC1 Channel 2            |
+---------------+-----------------+---------------------------+

System Clock
============
+4 −0
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@@ -72,3 +72,7 @@ arduino_serial: &lpuart1 {};
zephyr_udc0: &usb1 {
	status = "okay";
};

&adc1 {
	status = "okay";
};
+1 −0
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@@ -20,3 +20,4 @@ supported:
  - counter
  - usb_device
  - spi
  - adc
+13 −0
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@@ -101,6 +101,19 @@ static int mimxrt1010_evk_init(const struct device *dev)
			IOMUXC_SW_PAD_CTL_PAD_DSE(4));
#endif

#if DT_NODE_HAS_STATUS(DT_NODELABEL(adc1), okay) && CONFIG_ADC
	/* ADC Channels 1 and 2, exposed as pins 10 and 12 on J26 of EVK */
	IOMUXC_SetPinMux(IOMUXC_GPIO_AD_01_GPIOMUX_IO15, 0U);
	IOMUXC_SetPinMux(IOMUXC_GPIO_AD_02_GPIOMUX_IO16, 0U);

	IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_01_GPIOMUX_IO15,
				IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
				IOMUXC_SW_PAD_CTL_PAD_DSE(4));
	IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_02_GPIOMUX_IO16,
				IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
				IOMUXC_SW_PAD_CTL_PAD_DSE(4));
#endif

	return 0;
}

+12 −0
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/*
 * SPDX-License-Identifier: Apache-2.0
 *
 * Copyright (c) 2021 NXP
 */

/ {
	zephyr,user {
		/* adjust channel number according to pinmux in board.dts */
		io-channels = <&adc1 1>;
	};
};
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