Commit b0d613d9 authored by Daniel DeGrasse's avatar Daniel DeGrasse Committed by Carles Cufi
Browse files

boards: mimxrt1024_evk: Add ADC support to RT1024 



Adds ADC support to RT1024 EVK. ADC channels 10 and 11 are enabled as
pins 2 and 4 on J18 of the evaluation board

Signed-off-by: default avatarDaniel DeGrasse <daniel.degrasse@nxp.com>
parent 19983e60

boards/arm/mimxrt1024_evk/doc/index.rst

+6 −0
Original line number Diff line number Diff line
@@ -97,6 +97,8 @@ features: 
+-----------+------------+-------------------------------------+

| DMA       | on-chip    | dma                                 |

+-----------+------------+-------------------------------------+

| ADC       | on-chip    | adc                                 |

+-----------+------------+-------------------------------------+



The default configuration can be found in the defconfig file:

``boards/arm/mimxrt1024_evk/mimxrt1024_evk_defconfig``
@@ -151,6 +153,10 @@ The MIMXRT1024 SoC has five pairs of pinmux/gpio controllers. 
+---------------+-----------------+---------------------------+

| GPIO_SD_B1_03 | LPI2C4_SDA      | I2C SDA                   |

+---------------+-----------------+---------------------------+

| GPIO_AD_B1_11 | ADC1            | ADC1 Channel 11           |

+---------------+-----------------+---------------------------+

| GPIO_AD_B1_10 | ADC1            | ADC1 Channel 10           |

+---------------+-----------------+---------------------------+



System Clock

============

boards/arm/mimxrt1024_evk/mimxrt1024_evk.dts

+4 −0
Original line number Diff line number Diff line
@@ -120,3 +120,7 @@ 
&lpspi1 {

	status = "okay";

};



&adc1 {

	status = "okay";

};

boards/arm/mimxrt1024_evk/mimxrt1024_evk.yaml

+1 −0
Original line number Diff line number Diff line
@@ -21,3 +21,4 @@ supported: 
  - netif:eth

  - watchdog

  - spi

  - adc

boards/arm/mimxrt1024_evk/pinmux.c

+16 −0
Original line number Diff line number Diff line
@@ -147,6 +147,22 @@ static int mimxrt1024_evk_init(const struct device *dev) 
			IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |

			IOMUXC_SW_PAD_CTL_PAD_DSE(6));

#endif

#endif



#if DT_NODE_HAS_STATUS(DT_NODELABEL(adc1), okay) && CONFIG_ADC

	/* ADC1 Channel 10 and 11 are on pins 2 and 4 of J18 */

	/* ADC1 Channel 10 */

	IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_10_GPIO1_IO26, 0U);

	/* ADC1 Channel 11 */

	IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_11_GPIO1_IO27, 0U);



	IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_10_GPIO1_IO26,

			IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |

			IOMUXC_SW_PAD_CTL_PAD_DSE(6));

	IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_11_GPIO1_IO27,

			IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |

			IOMUXC_SW_PAD_CTL_PAD_DSE(6));



#endif



	return 0;

samples/drivers/adc/boards/mimxrt1024_evk.overlay

0 → 100644
+12 −0
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/*

 * SPDX-License-Identifier: Apache-2.0

 *

 * Copyright (c) 2021 NXP

 */



/ {

	zephyr,user {

		/* adjust channel number according to pinmux in board.dts */

		io-channels = <&adc1 10>;

	};

};

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