soc/intel_adsp: Keep track of started CPUs in the SOC layer

On cAVS 2.5, there is an inherent race with the IDC interrupt.  It's
used for routine IPIs during OS operation, but also for launching a
power-gated core.  Recent changes moved the unmasking of the IDC
interrupt earlier, which made it possible for early OS scheduler
behavior (e.g. adding the main thread to the run queue) to
accidentally launch the other cores into LP-SRAM that had not been
initialized.

Instead of treating this with initialization ordering, keep and
maintain a list of active CPUs and check them at runtime to be sure we
never try to IPI a CPU that isn't running yet.  We're going to need
this feature when we add live core offlining anyway.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>