soc: arm: cypress: Fix psoc6 irq priority

PSoC-6 have different priority bit masks for cortex-m0+ and cortex-m4.

M0: 0-3 (2 bits of NVIC prio, no prio reserved by the kernel)
M4: 0-6 (3 bits of NVIC prio, one level reserved by the kernel)

The current macro that gets priority level value from devicetree apply
same value from cortex-m4 on cortex-m0+.  This add missing indirection
to get from intmux node the correct cortex-m0+ priority level value.

Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>