dts: xilinx: Add PS GPIO controller and banks to Zynq-7000/ZynqMP DTs

Add the parent controller device node plus the child nodes for all
GPIO pin banks managed by the GPIO controller to the device trees
of the Zynq-7000 and ZynqMP SoCs.

Device base addresses, IRQ lines, number of banks, number of pins
per bank and bank descriptions taken from the Zynq-7000 TRM (Xilinx
document ID ug585), the Zynq UltraScale+ TRM (Xilinx document ID
ug1085) and the Zynq UltraScale+ Devices Register Reference (Xilinx
document ID ug1087, web-based document).

Signed-off-by: Immo Birnbaum <Immo.Birnbaum@weidmueller.com>