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Commit 9ae310b9 authored by Mahesh Mahadevan's avatar Mahesh Mahadevan Committed by Benjamin Cabé
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soc: nxp_mxrt7xx: Fix cache implementation for CPU0 



This SoC has an external XCACHE controller for CPU0
instruction and data bus.
Add code to enable the data cache. Instruction cache
is already enabled by SystemInit.

Signed-off-by: default avatarMahesh Mahadevan <mahesh.mahadevan@nxp.com>
parent b783bc84
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