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Commit 9abc29e3 authored by Simon Desfarges's avatar Simon Desfarges Committed by Gerrit Code Review
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arc_timer: assert that counter always lower than limit 



ASSERT are put each time the timer0 limit register or the timer0 count register
is modified.

Change-Id: I38684d57803de285f4e26c68b449c71396e4c750
Signed-off-by: default avatarSimon Desfarges <simon.desfarges@intel.com>
parent 5cecd07b
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