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Commit 985d49c1 authored by Khaoula Bidani's avatar Khaoula Bidani Committed by Johan Hedberg
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drivers: clock_control: fix PLL input frequency



Updated the PLL input frequency calculation to include
division by the HSI clock divider.
Enable HSI divider using LL_RCC_HSI_EnableDivider().

Signed-off-by: default avatarKhaoula Bidani <khaoula.bidani-ext@st.com>
parent 11c08264
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