drivers: intc: intc_cavs: use correct per-core register set for all ops

Current code uses per-core register to check interrupt status and
dispatch handlers. However to disable/enable the interrupt, core
zero register is always used.

While the handlers in _sw_isr_table are common for all cores,
the status bits should still be handled separate for each core.

Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>