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Commit 8f82cb08 authored by Yves Wang's avatar Yves Wang Committed by Benjamin Cabé
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dts: arm: nxp: Correct frdm_mcxw71 wdog default clock 



Watchdog clock source is 32K_CLK
Clock divider should be 1

Signed-off-by: default avatarYves Wang <zhengjia.wang@nxp.com>
parent dd0d6899
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