Skip to content
Commit 8b7ec919 authored by Dylan Hung's avatar Dylan Hung Committed by Carles Cufí
Browse files

soc: arm: aspeed: enable cache for AST10x0 series SOC 



Enable cache for AST10x0 series SOC in platform initialization.

Signed-off-by: default avatarDylan Hung <dylan_hung@aspeedtech.com>
parent 1c3810de
Show whitespace changes
Inline Side-by-side
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Please to comment

CRA Git | Maintained and supported by SUSTech CRA and CCSE