dts/bindigns/clock: allow stm32u5 DIVQ & DIVR PLL divider values to be 1

This commit changes the range for stm32u5 pll divider values
to allow divider value of 1.
- DIVQ is allowed to beconfigured 1 for all PLL instances
- DIVR can be 1 for PLL2 and PLL3, but is not valid for PLl1.

Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>