Skip to content
Commit 8a79ce14 authored by Daniel Leung's avatar Daniel Leung Committed by Andrew Boie
Browse files

riscv: add support for thread local storage 



Adds the necessary bits to initialize TLS in the stack
area and sets up CPU registers during context switch.

Signed-off-by: default avatarDaniel Leung <daniel.leung@intel.com>
parent 38872587
Show whitespace changes
Inline Side-by-side
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Please to comment

CRA Git | Maintained and supported by SUSTech CRA and CCSE