boards: nucleo_f070rb/f303re: fix clock configuration (897b5bf6) · Commits · Wenxi XU / zephyr

boards/arm/nucleo_f070rb/nucleo_f070rb_defconfig

+6 −4

Changes for boards/arm/nucleo_f070rb/nucleo_f070rb_defconfig: 6 added lines, 4 removed lines.
Original line number	Diff line number	Diff line
		@@ -25,14 +25,16 @@ CONFIG_GPIO=y
		# Clock configuration
		CONFIG_CLOCK_CONTROL=y
		# SYSCLK selection
		CONFIG_CLOCK_STM32_HSE_CLOCK=8000000
		CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y
		# PLL configuration
		CONFIG_CLOCK_STM32_PLL_SRC_HSE=y
		# HSE configuration
		CONFIG_CLOCK_STM32_HSE_CLOCK=8000000
		# however, the board does not have an external oscillator, so just use
		# the 8MHz clock signal coming from integrated STLink
		CONFIG_CLOCK_STM32_HSE_BYPASS=y

		# PLL configuration
		CONFIG_CLOCK_STM32_PLL_SRC_HSE=y
		# produce 48MHz clock at PLL output
		CONFIG_CLOCK_STM32_PLL_PREDIV1=1
		CONFIG_CLOCK_STM32_PLL_MULTIPLIER=6
		CONFIG_CLOCK_STM32_AHB_PRESCALER=1
		CONFIG_CLOCK_STM32_APB1_PRESCALER=1

+1 −1

Changes for boards/arm/nucleo_f303re/nucleo_f303re_defconfig: 1 added line, 1 removed line.
Original line number	Diff line number	Diff line
		@@ -32,7 +32,7 @@ CONFIG_CLOCK_STM32_PLL_SRC_HSE=y
		# the 8MHz clock signal coming from integrated STLink
		CONFIG_CLOCK_STM32_HSE_BYPASS=y
		# produce 72MHz clock at PLL output
		CONFIG_CLOCK_STM32_PLL_PREDIV=1
		CONFIG_CLOCK_STM32_PLL_PREDIV1=1
		CONFIG_CLOCK_STM32_PLL_MULTIPLIER=9
		CONFIG_CLOCK_STM32_AHB_PRESCALER=1
		CONFIG_CLOCK_STM32_APB1_PRESCALER=2