Commit 893eea6c authored by Parthiban Veerasooran's avatar Parthiban Veerasooran Committed by Chris Friedt
Browse files

drivers: ethernet: phy: microchip_t1s: fix missing MDIO bus enable/disable 



Call mdio_bus_enable() and mdio_bus_disable() during clause 22 register
read/write operations. Previously, these APIs were not invoked, which
could lead to improper MDIO bus handling.

This issue was observed during testing with the evb-lan8670-rmii
(an external LAN8670 PHY) connected to the SAME54 Curiosity Ultra
platform.

Signed-off-by: default avatarParthiban Veerasooran <parthiban.veerasooran@microchip.com>
parent c41cde79

drivers/ethernet/phy/phy_microchip_t1s.c

+32 −4
Original line number Diff line number Diff line
@@ -107,18 +107,32 @@ struct mc_t1s_data { 
static int phy_mc_t1s_read(const struct device *dev, uint16_t reg, uint32_t *data)

{

	const struct mc_t1s_config *cfg = dev->config;

	int ret;



	/* Make sure excessive bits 16-31 are reset */

	*data = 0U;



	return mdio_read(cfg->mdio, cfg->phy_addr, reg, (uint16_t *)data);

	mdio_bus_enable(cfg->mdio);



	ret = mdio_read(cfg->mdio, cfg->phy_addr, reg, (uint16_t *)data);



	mdio_bus_disable(cfg->mdio);



	return ret;

}



static int phy_mc_t1s_write(const struct device *dev, uint16_t reg, uint32_t data)

{

	const struct mc_t1s_config *cfg = dev->config;

	int ret;



	mdio_bus_enable(cfg->mdio);



	ret = mdio_write(cfg->mdio, cfg->phy_addr, reg, (uint16_t)data);



	mdio_bus_disable(cfg->mdio);



	return mdio_write(cfg->mdio, cfg->phy_addr, reg, (uint16_t)data);

	return ret;

}



static int mdio_setup_c45_indirect_access(const struct device *dev, uint16_t devad, uint16_t reg)
@@ -150,13 +164,20 @@ static int phy_mc_t1s_c45_read(const struct device *dev, uint8_t devad, uint16_t 
		return mdio_read_c45(cfg->mdio, cfg->phy_addr, devad, reg, val);

	}



	mdio_bus_enable(cfg->mdio);



	/* Read C45 registers using C22 indirect access registers */

	ret = mdio_setup_c45_indirect_access(dev, devad, reg);

	if (ret) {

		mdio_bus_disable(cfg->mdio);

		return ret;

	}



	return mdio_read(cfg->mdio, cfg->phy_addr, MII_MMD_AADR, val);

	ret = mdio_read(cfg->mdio, cfg->phy_addr, MII_MMD_AADR, val);



	mdio_bus_disable(cfg->mdio);



	return ret;

}



static int phy_mc_t1s_c45_write(const struct device *dev, uint8_t devad, uint16_t reg, uint16_t val)
@@ -170,13 +191,20 @@ static int phy_mc_t1s_c45_write(const struct device *dev, uint8_t devad, uint16_ 
		return mdio_write_c45(cfg->mdio, cfg->phy_addr, devad, reg, val);

	}



	mdio_bus_enable(cfg->mdio);



	/* Write C45 registers using C22 indirect access registers */

	ret = mdio_setup_c45_indirect_access(dev, devad, reg);

	if (ret) {

		mdio_bus_disable(cfg->mdio);

		return ret;

	}



	return mdio_write(cfg->mdio, cfg->phy_addr, MII_MMD_AADR, val);

	ret = mdio_write(cfg->mdio, cfg->phy_addr, MII_MMD_AADR, val);



	mdio_bus_disable(cfg->mdio);



	return ret;

}



static int phy_mc_t1s_get_link(const struct device *dev, struct phy_link_state *state)

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