soc: st: stm32: hsem: update description for fifth HSEM (86c51359) · Commits · Wenxi XU / zephyr

The fifth HSEM (#define is equal to 4 due to zero-indexing) is used on STM32H7 to synchronize the two cores. Update the comment above the SEMID define to reflect this alternate usage. Also remove the associated define CFG_HW_ENTRY_STOP_MODE_MASK_SEMID, which is unused. Signed-off-by:

Mathieu Choplain <mathieu.choplain@st.com>

soc/st/stm32/common/stm32_hsem.h

+6 −2

Changes for soc/st/stm32/common/stm32_hsem.h: 6 added lines, 2 removed lines.
Original line number	Diff line number	Diff line
		@@ -28,9 +28,13 @@
		/* Index of the semaphore used to access the RCC */
		#define CFG_HW_RCC_SEMID 3U

		/* Index of the semaphore used to manage the entry Stop Mode procedure */
		/**
		* Index of the semaphore used to manage the entry Stop Mode procedure.
		* On STM32H7, this semaphore is instead used to gate the Cortex-M4 core
		* until Cortex-M7 has finished initializing the system, and remains owned
		* by CM7 afterwards.
		*/
		#define CFG_HW_ENTRY_STOP_MODE_SEMID 4U
		#define CFG_HW_ENTRY_STOP_MODE_MASK_SEMID (1U << CFG_HW_ENTRY_STOP_MODE_SEMID)

		/**
		* Index of the semaphore used to manage the CLK48 clock configuration

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