Commit 97e2dd28 authored by Mathieu Choplain's avatar Mathieu Choplain Committed by Benjamin Cabé
Browse files

soc: st: stm32: hsem: sort hardware semaphore IDs by value 

Reorder the HSEM semaphore ID definitions to be sorted by ascending value.
The dummy defines are also changed to be sorted in the same order. The
definitions for STM32MP1 are already in an order that follows this order
so they don't need to be changed.

Signed-off-by: default avatarMathieu Choplain <mathieu.choplain@st.com>
parent a92339b8

soc/st/stm32/common/stm32_hsem.h

+44 −43
Changes for soc/st/stm32/common/stm32_hsem.h: 44 added lines, 43 removed lines.
Original line number Diff line number Diff line
@@ -11,30 +11,26 @@ 
#include <zephyr/kernel.h>



#if defined(CONFIG_SOC_SERIES_STM32WBX) || defined(CONFIG_STM32H7_DUAL_CORE)

/** HW semaphore Complement ID list defined in hw_conf.h from STM32WB

 * and used also for H7 dualcore targets

 */

/**

 *  Index of the semaphore used by CPU2 to prevent the CPU1 to either write or

 *  erase data in flash. The CPU1 shall not either write or erase in flash when

 *  this semaphore is taken by the CPU2. When the CPU1 needs to either write or

 *  erase in flash, it shall first get the semaphore and release it just

 *  after writing a raw (64bits data) or erasing one sector.

 *  On v1.4.0 and older CPU2 wireless firmware, this semaphore is unused and

 *  CPU2 is using PES bit. By default, CPU2 is using the PES bit to protect its

 *  timing. The CPU1 may request the CPU2 to use the semaphore instead of the

 *  PES bit by sending the system command SHCI_C2_SetFlashActivityControl()

 * Hardware semaphore assignment as defined in hw_conf.h from STM32WB.

 * These assignments are also used on H7 dual-core targets.

 */

#define CFG_HW_BLOCK_FLASH_REQ_BY_CPU2_SEMID                    7U



/**

 *  Index of the semaphore used by CPU1 to prevent the CPU2 to either write or

 *  erase data in flash. In order to protect its timing, the CPU1 may get this

 *  semaphore to prevent the  CPU2 to either write or erase in flash

 *  (as this will stall both CPUs)

 *  The PES bit shall not be used as this may stall the CPU2 in some cases.

 */

#define CFG_HW_BLOCK_FLASH_REQ_BY_CPU1_SEMID                    6U

/* Index of the semaphore used to access the RNG */

#define CFG_HW_RNG_SEMID                                        0U



/* Index of the semaphore used to access the PKA */

#define CFG_HW_PKA_SEMID                                        1U



/* Index of the semaphore used to access the FLASH */

#define CFG_HW_FLASH_SEMID                                      2U



/* Index of the semaphore used to access the RCC */

#define CFG_HW_RCC_SEMID                                        3U



/* Index of the semaphore used to manage the entry Stop Mode procedure */

#define CFG_HW_ENTRY_STOP_MODE_SEMID                            4U

#define CFG_HW_ENTRY_STOP_MODE_MASK_SEMID   (1U << CFG_HW_ENTRY_STOP_MODE_SEMID)



/**

 *  Index of the semaphore used to manage the CLK48 clock configuration
@@ -47,21 +43,27 @@ 
#define CFG_HW_CLK48_CONFIG_SEMID                               5U

#define CFG_HW_RCC_CRRCR_CCIPR_SEMID     CFG_HW_CLK48_CONFIG_SEMID



/* Index of the semaphore used to manage the entry Stop Mode procedure */

#define CFG_HW_ENTRY_STOP_MODE_SEMID                            4U

#define CFG_HW_ENTRY_STOP_MODE_MASK_SEMID   (1U << CFG_HW_ENTRY_STOP_MODE_SEMID)



/* Index of the semaphore used to access the RCC */

#define CFG_HW_RCC_SEMID                                        3U



/* Index of the semaphore used to access the FLASH */

#define CFG_HW_FLASH_SEMID                                      2U



/* Index of the semaphore used to access the PKA */

#define CFG_HW_PKA_SEMID                                        1U

/**

 *  Index of the semaphore used by CPU1 to prevent the CPU2 to either write or

 *  erase data in flash. In order to protect its timing, the CPU1 may get this

 *  semaphore to prevent the  CPU2 to either write or erase in flash

 *  (as this will stall both CPUs)

 *  The PES bit shall not be used as this may stall the CPU2 in some cases.

 */

#define CFG_HW_BLOCK_FLASH_REQ_BY_CPU1_SEMID                    6U



/* Index of the semaphore used to access the RNG */

#define CFG_HW_RNG_SEMID                                        0U

/**

 *  Index of the semaphore used by CPU2 to prevent the CPU1 to either write or

 *  erase data in flash. The CPU1 shall not either write or erase in flash when

 *  this semaphore is taken by the CPU2. When the CPU1 needs to either write or

 *  erase in flash, it shall first get the semaphore and release it just

 *  after writing a raw (64bits data) or erasing one sector.

 *  On v1.4.0 and older CPU2 wireless firmware, this semaphore is unused and

 *  CPU2 is using PES bit. By default, CPU2 is using the PES bit to protect its

 *  timing. The CPU1 may request the CPU2 to use the semaphore instead of the

 *  PES bit by sending the system command SHCI_C2_SetFlashActivityControl()

 */

#define CFG_HW_BLOCK_FLASH_REQ_BY_CPU2_SEMID                    7U



/** Index of the semaphore used to access GPIO */

#define CFG_HW_GPIO_SEMID                                       8U
@@ -89,15 +91,14 @@ 


#else

/** Fake semaphore ID definition for compilation purpose only */

#define CFG_HW_BLOCK_FLASH_REQ_BY_CPU2_SEMID  0U

#define CFG_HW_BLOCK_FLASH_REQ_BY_CPU1_SEMID  0U

#define CFG_HW_CLK48_CONFIG_SEMID             0U

#define CFG_HW_RCC_CRRCR_CCIPR_SEMID          0U

#define CFG_HW_ENTRY_STOP_MODE_SEMID          0U

#define CFG_HW_RCC_SEMID                      0U

#define CFG_HW_FLASH_SEMID                    0U

#define CFG_HW_PKA_SEMID                      0U

#define CFG_HW_RNG_SEMID			0U

#define CFG_HW_PKA_SEMID			0U

#define CFG_HW_FLASH_SEMID			0U

#define CFG_HW_RCC_SEMID			0U

#define CFG_HW_ENTRY_STOP_MODE_SEMID		0U

#define CFG_HW_CLK48_CONFIG_SEMID		0U

#define CFG_HW_BLOCK_FLASH_REQ_BY_CPU1_SEMID	0U

#define CFG_HW_BLOCK_FLASH_REQ_BY_CPU2_SEMID	0U

#define CFG_HW_GPIO_SEMID			0U

#define CFG_HW_EXTI_SEMID			0U

#define CFG_HW_IPM_CPU1_SEMID			0U

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