intel_adsp: clk: Configure correct cardinal clock divider for PTL

The Audio integration PLL is faster on PTL compared to earlier ACE
platforms: 442.368 MHz instead 393.216 MHz, however the default
divider remained 16, which will result incorrect cardinal clock speed.

Change the divider to 18 in order to get correct 24.576 MHz cardinal
clock.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@linux.intel.com>