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Commit 82ce2b41 authored by Daniel DeGrasse's avatar Daniel DeGrasse Committed by Alberto Escolar
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sd: sdmmc: rework frequency and timing selection logic



SDMMC framework frequency and timing selection logic has several
longstanding issues, including:
- requiring that SD hosts support the maximum frequency possible for a
  given UHS mode in order to apply that timing
- selecting SDHC_TIMING_SDR25 for high speed mode, when SDHC_TIMING_HS
  would be correct

Rework the frequency and timing selection logic within the SD framework
to resolve these issues.

Fixes #52589
Fixes #67943

Signed-off-by: default avatarDaniel DeGrasse <daniel.degrasse@nxp.com>
parent 87030f4c
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