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Commit 82c2f388 authored by Jimmy Zheng's avatar Jimmy Zheng Committed by Fabio Baltieri
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tests: kernel: gen_isr_table.riscv_direct: exclude adp_xc7k_ae350 



Exclude adp_xc7k_ae350 because Andes core doesn't support RISC-V vectored
mode from csr $mtvec.

Signed-off-by: default avatarJimmy Zheng <jimmyzhe@andestech.com>
parent e6b1251b
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