drivers: spi: ensure the first byte has been loaded in the TX fast path

The SAM0 has a data register and a shift register.  Data that is
written to the data register is transferred to the shift register by
the peripheral.

On the SAMD51, the CPU is fast enough that the first data write hasn't
been transferred to the shift register by the time the next data write
occurs, causing the second write to be dropped, causing the receiver
to wait forever.

Fix by spinning until the data register is empty.

Signed-off-by: Michael Hope <mlhx@google.com>