soc: riscv: andes_v5: add custom CSR context switch support

Support custom RISC-V CSR context switch for Andes V5 CPUs.
Both AndeStar V5 DSP and PowerBrake features have it's own CSR to be
saved for thread and ISR context, so adding these CSRs into the RISC-V
SOC context management framework (CONFIG_RISCV_SOC_CONTEXT_SAVE).

Signed-off-by: Jim Shu <cwshu@andestech.com>