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Commit 7b601b7f authored by Michal Sieron's avatar Michal Sieron Committed by Marti Bolivar
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dts: riscv: litex-vexriscv: Fix clock node address 



Also change its register indentation from spaces to tabs

Signed-off-by: default avatarMichal Sieron <msieron@internships.antmicro.com>
parent dc98691c
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