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Commit 7a276208 authored by Robert Hancock's avatar Robert Hancock Committed by Benjamin Cabé
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soc: xlnx: zynqmp: Enable I/D caches 



On ZynqMP, the RPU Cortex-R5 cores come up by default without
instruction and data caches enabled. Enable them as part of
soc_early_init_hook when CONFIG_CACHE_MANAGEMENT is enabled.

Signed-off-by: default avatarRobert Hancock <robert.hancock@calian.com>
parent e36d4faf
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