Commit 7514a92c authored by Kumar Gala's avatar Kumar Gala Committed by Kumar Gala
Browse files

arch: arm: nxp_lpc: Added support for init of slave core 



Added ability to load and bootup the slave (Cortex-M0+) core on the
LPC54xxx SoC.  Currently we expect a binary image to be specified via
Kconfig for the code that will run on the slave core.  We also specify
via Kconfig the boot/load address for the slave core.

Origin: Original

Signed-off-by: default avatarStanislav Poboril <stanislav.poboril@nxp.com>
Signed-off-by: default avatarKumar Gala <kumar.gala@linaro.org>
parent b7312d1b

arch/arm/soc/nxp_lpc/lpc54xxx/CMakeLists.txt

+14 −3
Original line number Diff line number Diff line
@@ -3,7 +3,18 @@ 
#

# SPDX-License-Identifier: Apache-2.0

#

zephyr_library()



zephyr_sources(

  soc.c

  )
 
zephyr_library_sources(soc.c)



if (CONFIG_SLAVE_CORE_MCUX)

  set(gen_dir ${ZEPHYR_BINARY_DIR}/include/generated/)

  string(CONFIGURE ${CONFIG_SLAVE_IMAGE_MCUX} core_m0_image)



  add_custom_target(core_m0_inc_target DEPENDS ${gen_dir}/core-m0.inc)



  generate_inc_file_for_gen_target(${ZEPHYR_CURRENT_LIBRARY}

				   ${core_m0_image}

				   ${gen_dir}/core-m0.inc

				   core_m0_inc_target)

endif()

arch/arm/soc/nxp_lpc/lpc54xxx/Kconfig.soc

+23 −0
Original line number Diff line number Diff line
@@ -35,4 +35,27 @@ config SOC_PART_NUMBER_LPC54XXX 
	  option that you should not set directly. The part number selection

	  choice defines the default value for this string.



config SLAVE_CORE_MCUX

	bool "Enable LPC54114 Cortex-M0 slave core"

	default n

	depends on HAS_MCUX

	help

	  Driver for slave core startup



config SLAVE_IMAGE_MCUX

	depends on SLAVE_CORE_MCUX

	string "Binary image of slave core's code"

	help

	  This points to the image file for the the binary code that will be

	  used by the slave core.



config SLAVE_BOOT_ADDRESS_MCUX

	depends on SLAVE_CORE_MCUX

	hex "Address the slave core will boot at"

	default 0x20010000

	help

	  This is the address the slave core will boot from.  Additionally this

	  address is where we will copy the SLAVE_IMAGE to.  We default this to

	  the base of SRAM1



endif # SOC_SERIES_LPC54XXX

arch/arm/soc/nxp_lpc/lpc54xxx/soc.c

+58 −0
Original line number Diff line number Diff line
@@ -105,3 +105,61 @@ static int nxp_lpc54114_init(struct device *arg) 
}



SYS_INIT(nxp_lpc54114_init, PRE_KERNEL_1, 0);





#ifdef CONFIG_SLAVE_CORE_MCUX



#define CORE_M0_BOOT_ADDRESS (void *)CONFIG_SLAVE_BOOT_ADDRESS_MCUX



static const char core_m0[] = {

#include "core-m0.inc"

};



/**

 *

 * @brief Slave Init

 *

 * This routine boots the secondary core

 * @return N/A

 */

/* This function is also called at deep sleep resume. */

int _slave_init(struct device *arg)

{

	s32_t temp;



	ARG_UNUSED(arg);



	/* Enable SRAM2, used by other core */

	SYSCON->AHBCLKCTRLSET[0] = SYSCON_AHBCLKCTRL_SRAM2_MASK;



	/* Copy second core image to SRAM */

	memcpy(CORE_M0_BOOT_ADDRESS, (void *)core_m0, sizeof(core_m0));



	/* Setup the reset handler pointer (PC) and stack pointer value.

	 * This is used once the second core runs its startup code.

	 * The second core first boots from flash (address 0x00000000)

	 * and then detects its identity (Cortex-M0, slave) and checks

	 * registers CPBOOT and CPSTACK and use them to continue the

	 * boot process.

	 * Make sure the startup code for current core (Cortex-M4) is

	 * appropriate and shareable with the Cortex-M0 core!

	 */

	SYSCON->CPBOOT = SYSCON_CPBOOT_BOOTADDR(

			*(uint32_t *)((uint8_t *)CORE_M0_BOOT_ADDRESS + 0x4));

	SYSCON->CPSTACK = SYSCON_CPSTACK_STACKADDR(

			*(uint32_t *)CORE_M0_BOOT_ADDRESS);



	/* Reset the secondary core and start its clocks */

	temp = SYSCON->CPCTRL;

	temp |= 0xc0c48000;

	SYSCON->CPCTRL = (temp | SYSCON_CPCTRL_CM0CLKEN_MASK

					| SYSCON_CPCTRL_CM0RSTEN_MASK);

	SYSCON->CPCTRL = (temp | SYSCON_CPCTRL_CM0CLKEN_MASK)

					& (~SYSCON_CPCTRL_CM0RSTEN_MASK);



	return 0;

}



SYS_INIT(_slave_init, PRE_KERNEL_2, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);



#endif /*CONFIG_SLAVE_CORE_MCUX*/

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