Commit b7312d1b authored by Kumar Gala's avatar Kumar Gala Committed by Kumar Gala
Browse files

arch: arm: lpc: Added support for Cortex-M0+ on lpc54114 soc 



Add soc configuration support and dts files for nxp_lpc54xxx_m0.

Adjusted nxp_lpc54xxx soc, configuration and dts files for the
presence of slave core.

Origin: Original

Signed-off-by: default avatarStanislav Poboril <stanislav.poboril@nxp.com>
Signed-off-by: default avatarKumar Gala <kumar.gala@linaro.org>
parent cc8b7265

arch/arm/soc/nxp_lpc/lpc54xxx/Kconfig.defconfig.lpc54114_m0

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+39 −0
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# Kconfig - NXP LPC54114 M0 platform configuration options



#

# Copyright (c) 2017, NXP

#

# SPDX-License-Identifier: Apache-2.0

#



if SOC_LPC54114_M0



config SOC

	string

	default lpc54114_m0



if PINMUX



config PINMUX_MCUX_LPC

	def_bool n



endif # PINMUX



config GPIO

	def_bool n



if GPIO



config GPIO_MCUX_LPC

	def_bool n



endif # GPIO



if SERIAL



config USART_MCUX_LPC

	def_bool n



endif # SERIAL



endif # SOC_LPC54114_M0

arch/arm/soc/nxp_lpc/lpc54xxx/Kconfig.soc

+5 −0
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@@ -14,6 +14,11 @@ config SOC_LPC54114_M4 
	select CPU_CORTEX_M4

	select PLATFORM_SPECIFIC_INIT



config SOC_LPC54114_M0

	bool "SOC_LPC54114_M0"

	select CPU_CORTEX_M0PLUS

	select CPU_CORTEX_M_HAS_VTOR



endchoice



if SOC_SERIES_LPC54XXX

arch/arm/soc/nxp_lpc/lpc54xxx/dts.fixup

+4 −0
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@@ -6,7 +6,11 @@ 


/* SoC level DTS fixup file */



#if defined(CONFIG_SOC_LPC54114_M0)

#define CONFIG_NUM_IRQ_PRIO_BITS		ARM_V6M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS

#else

#define CONFIG_NUM_IRQ_PRIO_BITS		ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS

#endif



#define CONFIG_USART_MCUX_LPC_0_BASE_ADDRESS	NXP_LPC_USART_40086000_BASE_ADDRESS

#define CONFIG_USART_MCUX_LPC_0_BAUD_RATE	NXP_LPC_USART_40086000_CURRENT_SPEED

arch/arm/soc/nxp_lpc/lpc54xxx/soc.c

+3 −0
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@@ -35,6 +35,8 @@ 


static ALWAYS_INLINE void clkInit(void)

{



#ifdef CONFIG_SOC_LPC54114_M4

	/* Set up the clock sources */



	/* Ensure FRO is on */
@@ -62,6 +64,7 @@ static ALWAYS_INLINE void clkInit(void) 


	/* Attach 12 MHz clock to FLEXCOMM0 */

	CLOCK_AttachClk(kFRO12M_to_FLEXCOMM0);

#endif /* CONFIG_SOC_LPC54114_M4 */

}



/**

dts/arm/nxp/nxp_lpc54xxx_m0.dtsi

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/*

 * Copyright (c) 2017, NXP

 *

 * SPDX-License-Identifier: Apache-2.0

 */



#include <arm/armv6-m.dtsi>

#include <nxp/nxp_lpc54xxx.dtsi>



/ {

	cpus {

		/delete-node/ cpu@0;



		cpu@1 {

			compatible = "arm,cortex-m0+";

		};

	};

};



&nvic {

	arm,num-irq-priority-bits = <2>;

};

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