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Commit 73ab22e8 authored by Francois Ramu's avatar Francois Ramu Committed by Benjamin Cabé
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drivers: clock control of some stm32f4x has no 48MHz from PLL i2s 



Remove the LL_RCC_PLLI2S_ConfigDomain_48M for the stm32f4
w/o Q divider on the PLLI2S to configure the PLL48CK

Signed-off-by: default avatarFrancois Ramu <francois.ramu@st.com>
parent bba13ae2
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