boards: stm32h573i_dk: Fix CAN core clock

Set the PLL1_Q divider to 6 give a can core clock of 80MHz to
resolve fdcan_clk reception problem because M_CAN requires that
the host clock "APB1" should be higher or equal to the CAN core
clock "PLL1_Q".

Signed-off-by: IBEN EL HADJ MESSAOUD Marwa <marwa.ibenelhadjmessaoud-ext@st.com>