drivers: clock_control: stm32: Fixed domain clock configuration

In some case, we may need to describe a domain clock for a device
while there is no way to configure it (ex: USB clock set on PLL_Q output
on F405 devices > It is not selectable).
Then, configuring a device clock domain in the clock_control driver
will allow to retrieve its subsys rate.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>