Commit 64eb350e authored by Gerard Marull-Paretas's avatar Gerard Marull-Paretas Committed by Carles Cufi
Browse files

drivers: spi: gd32: use clock control API 

Use the clock control API to enable/get rate of SPI clocks.

Signed-off-by: default avatarGerard Marull-Paretas <gerard@teslabs.com>
parent 0aadc2dd

drivers/spi/spi_gd32.c

+9 −22
Changes for drivers/spi/spi_gd32.c: 9 added lines, 22 removed lines.
Original line number Diff line number Diff line
@@ -8,11 +8,12 @@ 


#include <errno.h>

#include <zephyr/kernel.h>

#include <zephyr/drivers/clock_control.h>

#include <zephyr/drivers/clock_control/gd32.h>

#include <zephyr/drivers/pinctrl.h>

#include <zephyr/drivers/reset.h>

#include <zephyr/drivers/spi.h>



#include <gd32_rcu.h>

#include <gd32_spi.h>



#include <zephyr/logging/log.h>
@@ -35,13 +36,9 @@ LOG_MODULE_REGISTER(spi_gd32); 
#else

#error Unknown GD32 soc series

#endif



/* Obtain RCU register offset from RCU clock value */

#define RCU_CLOCK_OFFSET(rcu_clock) ((rcu_clock) >> 6U)



struct spi_gd32_config {

	uint32_t reg;

	uint32_t rcu_periph_clock;

	uint16_t clkid;

	struct reset_dt_spec reset;

	const struct pinctrl_dev_config *pcfg;

#ifdef CONFIG_SPI_GD32_INTERRUPT
@@ -73,19 +70,6 @@ static bool spi_gd32_transfer_ongoing(struct spi_gd32_data *data) 
	       spi_context_rx_on(&data->ctx);

}



static uint32_t spi_gd32_bus_freq_get(uint32_t rcu_periph_clock)

{

	uint32_t rcu_bus;



	if (RCU_CLOCK_OFFSET(rcu_periph_clock) == RCU_APB1EN_OFFSET) {

		rcu_bus = CK_APB1;

	} else {

		rcu_bus = CK_APB2;

	}



	return rcu_clock_freq_get(rcu_bus);

}



static int spi_gd32_configure(const struct device *dev,

			      const struct spi_config *config)

{
@@ -140,7 +124,9 @@ static int spi_gd32_configure(const struct device *dev, 
		SPI_CTL0(cfg->reg) |= SPI_CTL0_CKPH;

	}



	bus_freq = spi_gd32_bus_freq_get(cfg->rcu_periph_clock);

	(void)clock_control_get_rate(GD32_CLOCK_CONTROLLER,

				     (clock_control_subsys_t *)&cfg->clkid,

				     &bus_freq);



	for (uint8_t i = 0U; i <= GD32_SPI_PSC_MAX; i++) {

		bus_freq = bus_freq >> 1U;
@@ -341,7 +327,8 @@ int spi_gd32_init(const struct device *dev) 
	const struct spi_gd32_config *cfg = dev->config;

	int ret;



	rcu_periph_clock_enable(cfg->rcu_periph_clock);

	(void)clock_control_on(GD32_CLOCK_CONTROLLER,

			       (clock_control_subsys_t *)&cfg->clkid);



	(void)reset_line_toggle_dt(&cfg->reset);
@@ -383,7 +370,7 @@ int spi_gd32_init(const struct device *dev) 
		SPI_CONTEXT_CS_GPIOS_INITIALIZE(DT_DRV_INST(idx), ctx) };      \

	static struct spi_gd32_config spi_gd32_config_##idx = {		       \

		.reg = DT_INST_REG_ADDR(idx),				       \

		.rcu_periph_clock = DT_INST_PROP(idx, rcu_periph_clock),       \

		.clkid = DT_INST_CLOCKS_CELL(idx, id),			       \

		.reset = RESET_DT_SPEC_INST_GET(idx),			       \

		.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(idx),		       \

		IF_ENABLED(CONFIG_SPI_GD32_INTERRUPT,			       \

dts/arm/gigadevice/gd32f403/gd32f403.dtsi

+3 −3
Changes for dts/arm/gigadevice/gd32f403/gd32f403.dtsi: 3 added lines, 3 removed lines.
Original line number Diff line number Diff line
@@ -115,7 +115,7 @@ 
			compatible = "gd,gd32-spi";

			reg = <0x40013000 0x400>;

			interrupts = <35 0>;

			rcu-periph-clock = <0x60c>;

			clocks = <&cctl GD32_CLOCK_SPI0>;

			resets = <&rctl GD32_RESET_SPI0>;

			status = "disabled";

			#address-cells = <1>;
@@ -126,7 +126,7 @@ 
			compatible = "gd,gd32-spi";

			reg = <0x40003800 0x400>;

			interrupts = <36 0>;

			rcu-periph-clock = <0x70e>;

			clocks = <&cctl GD32_CLOCK_SPI1>;

			resets = <&rctl GD32_RESET_SPI1>;

			status = "disabled";

			#address-cells = <1>;
@@ -137,7 +137,7 @@ 
			compatible = "gd,gd32-spi";

			reg = <0x40003c00 0x400>;

			interrupts = <51 0>;

			rcu-periph-clock = <0x70f>;

			clocks = <&cctl GD32_CLOCK_SPI2>;

			resets = <&rctl GD32_RESET_SPI2>;

			status = "disabled";

			#address-cells = <1>;

dts/arm/gigadevice/gd32f4xx/gd32f450.dtsi

+3 −3
Changes for dts/arm/gigadevice/gd32f4xx/gd32f450.dtsi: 3 added lines, 3 removed lines.
Original line number Diff line number Diff line
@@ -13,7 +13,7 @@ 
			compatible = "gd,gd32-spi";

			reg = <0x40013400 0x400>;

			interrupts = <84 0>;

			rcu-periph-clock = <0x110d>;

			clocks = <&cctl GD32_CLOCK_SPI3>;

			resets = <&rctl GD32_RESET_SPI3>;

			status = "disabled";

			#address-cells = <1>;
@@ -24,7 +24,7 @@ 
			compatible = "gd,gd32-spi";

			reg = <0x40015000 0x400>;

			interrupts = <85 0>;

			rcu-periph-clock = <0x1114>;

			clocks = <&cctl GD32_CLOCK_SPI4>;

			resets = <&rctl GD32_RESET_SPI4>;

			status = "disabled";

			#address-cells = <1>;
@@ -35,7 +35,7 @@ 
			compatible = "gd,gd32-spi";

			reg = <0x40015400 0x400>;

			interrupts = <86 0>;

			rcu-periph-clock = <0x1115>;

			clocks = <&cctl GD32_CLOCK_SPI5>;

			resets = <&rctl GD32_RESET_SPI5>;

			status = "disabled";

			#address-cells = <1>;

dts/arm/gigadevice/gd32f4xx/gd32f4xx.dtsi

+3 −3
Changes for dts/arm/gigadevice/gd32f4xx/gd32f4xx.dtsi: 3 added lines, 3 removed lines.
Original line number Diff line number Diff line
@@ -191,7 +191,7 @@ 
			compatible = "gd,gd32-spi";

			reg = <0x40013000 0x400>;

			interrupts = <35 0>;

			rcu-periph-clock = <0x110c>;

			clocks = <&cctl GD32_CLOCK_SPI0>;

			resets = <&rctl GD32_RESET_SPI0>;

			status = "disabled";

			#address-cells = <1>;
@@ -202,7 +202,7 @@ 
			compatible = "gd,gd32-spi";

			reg = <0x40003800 0x400>;

			interrupts = <36 0>;

			rcu-periph-clock = <0x100e>;

			clocks = <&cctl GD32_CLOCK_SPI1>;

			resets = <&rctl GD32_RESET_SPI1>;

			status = "disabled";

			#address-cells = <1>;
@@ -213,7 +213,7 @@ 
			compatible = "gd,gd32-spi";

			reg = <0x40003c00 0x400>;

			interrupts = <51 0>;

			rcu-periph-clock = <0x100f>;

			clocks = <&cctl GD32_CLOCK_SPI2>;

			resets = <&rctl GD32_RESET_SPI2>;

			status = "disabled";

			#address-cells = <1>;

dts/bindings/spi/gd,gd32-spi.yaml

+1 −3
Changes for dts/bindings/spi/gd,gd32-spi.yaml: 1 added line, 3 removed lines.
Original line number Diff line number Diff line
@@ -17,9 +17,7 @@ properties: 
  resets:

    required: true



  rcu-periph-clock:

    type: int

    description: Peripheral RCU(Reset Clock Unit) Clock ID

  clocks:

    required: true



  pinctrl-0:

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