Commit 0aadc2dd authored by Gerard Marull-Paretas's avatar Gerard Marull-Paretas Committed by Carles Cufi
Browse files

drivers: serial: gd32: use clock control API 

Use the clock control API to enable the UART clock.

Signed-off-by: default avatarGerard Marull-Paretas <gerard@teslabs.com>
parent 22e64fdd

drivers/serial/usart_gd32.c

+7 −4
Changes for drivers/serial/usart_gd32.c: 7 added lines, 4 removed lines.
Original line number Diff line number Diff line
@@ -6,12 +6,14 @@ 
#define DT_DRV_COMPAT gd_gd32_usart



#include <errno.h>



#include <zephyr/drivers/clock_control.h>

#include <zephyr/drivers/clock_control/gd32.h>

#include <zephyr/drivers/pinctrl.h>

#include <zephyr/drivers/reset.h>

#include <zephyr/drivers/uart.h>



#include <gd32_usart.h>

#include <gd32_rcu.h>



/* Unify GD32 HAL USART status register name to USART_STAT */

#ifndef USART_STAT
@@ -20,7 +22,7 @@ 


struct gd32_usart_config {

	uint32_t reg;

	uint32_t rcu_periph_clock;

	uint16_t clkid;

	struct reset_dt_spec reset;

	const struct pinctrl_dev_config *pcfg;

	uint32_t parity;
@@ -82,7 +84,8 @@ static int usart_gd32_init(const struct device *dev) 
		return -ENOTSUP;

	}



	rcu_periph_clock_enable(cfg->rcu_periph_clock);

	(void)clock_control_on(GD32_CLOCK_CONTROLLER,

			       (clock_control_subsys_t *)&cfg->clkid);



	(void)reset_line_toggle_dt(&cfg->reset);
@@ -321,7 +324,7 @@ static const struct uart_driver_api usart_gd32_driver_api = { 
	};									\

	static const struct gd32_usart_config usart_gd32_config_##n = {		\

		.reg = DT_INST_REG_ADDR(n),					\

		.rcu_periph_clock = DT_INST_PROP(n, rcu_periph_clock),		\

		.clkid = DT_INST_CLOCKS_CELL(n, id),				\

		.reset = RESET_DT_SPEC_INST_GET(n),				\

		.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n),			\

		.parity = DT_INST_ENUM_IDX_OR(n, parity, UART_CFG_PARITY_NONE),	\

dts/arm/gigadevice/gd32e10x/gd32e10x.dtsi

+5 −5
Changes for dts/arm/gigadevice/gd32e10x/gd32e10x.dtsi: 5 added lines, 5 removed lines.
Original line number Diff line number Diff line
@@ -64,7 +64,7 @@ 
			compatible = "gd,gd32-usart";

			reg = <0x40013800 0x400>;

			interrupts = <37 0>;

			rcu-periph-clock = <0x60e>;

			clocks = <&cctl GD32_CLOCK_USART0>;

			resets = <&rctl GD32_RESET_USART0>;

			status = "disabled";

		};
@@ -73,7 +73,7 @@ 
			compatible = "gd,gd32-usart";

			reg = <0x40004400 0x400>;

			interrupts = <38 0>;

			rcu-periph-clock = <0x711>;

			clocks = <&cctl GD32_CLOCK_USART1>;

			resets = <&rctl GD32_RESET_USART1>;

			status = "disabled";

		};
@@ -82,7 +82,7 @@ 
			compatible = "gd,gd32-usart";

			reg = <0x40004800 0x400>;

			interrupts = <39 0>;

			rcu-periph-clock = <0x712>;

			clocks = <&cctl GD32_CLOCK_USART2>;

			resets = <&rctl GD32_RESET_USART2>;

			status = "disabled";

		};
@@ -91,7 +91,7 @@ 
			compatible = "gd,gd32-usart";

			reg = <0x40004c00 0x400>;

			interrupts = <52 0>;

			rcu-periph-clock = <0x713>;

			clocks = <&cctl GD32_CLOCK_UART3>;

			resets = <&rctl GD32_RESET_UART3>;

			status = "disabled";

		};
@@ -100,7 +100,7 @@ 
			compatible = "gd,gd32-usart";

			reg = <0x40005000 0x400>;

			interrupts = <53 0>;

			rcu-periph-clock = <0x714>;

			clocks = <&cctl GD32_CLOCK_UART4>;

			resets = <&rctl GD32_RESET_UART4>;

			status = "disabled";

		};

dts/arm/gigadevice/gd32e50x/gd32e50x.dtsi

+6 −6
Changes for dts/arm/gigadevice/gd32e50x/gd32e50x.dtsi: 6 added lines, 6 removed lines.
Original line number Diff line number Diff line
@@ -71,7 +71,7 @@ 
			compatible = "gd,gd32-usart";

			reg = <0x40013800 0x400>;

			interrupts = <37 0>;

			rcu-periph-clock = <0x60e>;

			clocks = <&cctl GD32_CLOCK_USART0>;

			resets = <&rctl GD32_RESET_USART0>;

			status = "disabled";

		};
@@ -80,7 +80,7 @@ 
			compatible = "gd,gd32-usart";

			reg = <0x40004400 0x400>;

			interrupts = <38 0>;

			rcu-periph-clock = <0x711>;

			clocks = <&cctl GD32_CLOCK_USART1>;

			resets = <&rctl GD32_RESET_USART1>;

			status = "disabled";

		};
@@ -89,7 +89,7 @@ 
			compatible = "gd,gd32-usart";

			reg = <0x40004800 0x400>;

			interrupts = <39 0>;

			rcu-periph-clock = <0x712>;

			clocks = <&cctl GD32_CLOCK_USART2>;

			resets = <&rctl GD32_RESET_USART2>;

			status = "disabled";

		};
@@ -98,7 +98,7 @@ 
			compatible = "gd,gd32-usart";

			reg = <0x40004c00 0x400>;

			interrupts = <52 0>;

			rcu-periph-clock = <0x713>;

			clocks = <&cctl GD32_CLOCK_UART3>;

			resets = <&rctl GD32_RESET_UART3>;

			status = "disabled";

		};
@@ -107,7 +107,7 @@ 
			compatible = "gd,gd32-usart";

			reg = <0x40005000 0x400>;

			interrupts = <53 0>;

			rcu-periph-clock = <0x714>;

			clocks = <&cctl GD32_CLOCK_UART4>;

			resets = <&rctl GD32_RESET_UART4>;

			status = "disabled";

		};
@@ -117,7 +117,7 @@ 
			reg = <0x40017000 0x400>;

			interrupts = <84 0>, <86 0>;

			interrupt-names = "global", "wkup";

			rcu-periph-clock = <0x61c>;

			clocks = <&cctl GD32_CLOCK_USART5>;

			resets = <&rctl GD32_RESET_USART5>;

			status = "disabled";

		};

dts/arm/gigadevice/gd32f3x0/gd32f3x0.dtsi

+2 −2
Changes for dts/arm/gigadevice/gd32f3x0/gd32f3x0.dtsi: 2 added lines, 2 removed lines.
Original line number Diff line number Diff line
@@ -62,7 +62,7 @@ 
			compatible = "gd,gd32-usart";

			reg = <0x40013800 0x400>;

			interrupts = <27 0>;

			rcu-periph-clock = <0x060e>;

			clocks = <&cctl GD32_CLOCK_USART0>;

			resets = <&rctl GD32_RESET_USART0>;

			status = "disabled";

		};
@@ -71,7 +71,7 @@ 
			compatible = "gd,gd32-usart";

			reg = <0x40004400 0x400>;

			interrupts = <28 0>;

			rcu-periph-clock = <0x0711>;

			clocks = <&cctl GD32_CLOCK_USART1>;

			resets = <&rctl GD32_RESET_USART1>;

			status = "disabled";

		};

dts/arm/gigadevice/gd32f403/gd32f403.dtsi

+5 −5
Changes for dts/arm/gigadevice/gd32f403/gd32f403.dtsi: 5 added lines, 5 removed lines.
Original line number Diff line number Diff line
@@ -70,7 +70,7 @@ 
			compatible = "gd,gd32-usart";

			reg = <0x40013800 0x400>;

			interrupts = <37 0>;

			rcu-periph-clock = <0x60e>;

			clocks = <&cctl GD32_CLOCK_USART0>;

			resets = <&rctl GD32_RESET_USART0>;

			status = "disabled";

		};
@@ -79,7 +79,7 @@ 
			compatible = "gd,gd32-usart";

			reg = <0x40004400 0x400>;

			interrupts = <38 0>;

			rcu-periph-clock = <0x712>;

			clocks = <&cctl GD32_CLOCK_USART1>;

			resets = <&rctl GD32_RESET_USART1>;

			status = "disabled";

		};
@@ -88,7 +88,7 @@ 
			compatible = "gd,gd32-usart";

			reg = <0x40004800 0x400>;

			interrupts = <39 0>;

			rcu-periph-clock = <0x713>;

			clocks = <&cctl GD32_CLOCK_USART2>;

			resets = <&rctl GD32_RESET_USART2>;

			status = "disabled";

		};
@@ -97,7 +97,7 @@ 
			compatible = "gd,gd32-usart";

			reg = <0x40004c00 0x400>;

			interrupts = <52 0>;

			rcu-periph-clock = <0x714>;

			clocks = <&cctl GD32_CLOCK_UART3>;

			resets = <&rctl GD32_RESET_UART3>;

			status = "disabled";

		};
@@ -106,7 +106,7 @@ 
			compatible = "gd,gd32-usart";

			reg = <0x40005000 0x400>;

			interrupts = <53 0>;

			rcu-periph-clock = <0x715>;

			clocks = <&cctl GD32_CLOCK_UART4>;

			resets = <&rctl GD32_RESET_UART4>;

			status = "disabled";

		};

CRA Git | Maintained and supported by SUSTech CRA and CCSE