drivers: clock_control: clock_control_ra.c: clock divider fix

The clock divider value is not being applied as the address of the
register to which it is being written is incorrect. A check of all RA MCU
datasheets confirms that, in all cases, the SCKDIVCR register is at an
offset of 0x20 (and not 0x21).

Signed-off-by: Ian Morris <ian.d.morris@outlook.com>