Commit 6299890b authored by Filip Kokosinski's avatar Filip Kokosinski Committed by Maureen Helm
Browse files

dts: riscv32: microsemi-miv: add flash and sram 



Add flash and SRAM to the Microsemi MiV device tree.

Signed-off-by: default avatarFilip Kokosinski <fkokosinski@internships.antmicro.com>
Signed-off-by: default avatarMateusz Holenko <mholenko@antmicro.com>
parent ff167995

dts/riscv32/microsemi-miv.dtsi

+11 −0
Original line number Diff line number Diff line
@@ -31,6 +31,17 @@ 
		compatible = "microsemi,miv-soc", "simple-bus";

		ranges;



		flash0: flash@80000000 {

			compatible = "soc-nv-flash";

			reg = <0x80000000 0x40000>;

		};



		sram0: memory@80040000 {

			device_type = "memory";

			compatible = "mmio-sram";

			reg = <0x80040000 0x40000>;

		};



		plic: interrupt-controller@40000000 {

			#interrupt-cells = <1>;

			compatible = "riscv,plic0";

CRA Git | Maintained and supported by SUSTech CRA and CCSE