tests: clock_control: stm32u5 device: Fix clk_msik configuration

In tests/drivers/clock_control/stm32_clock_configuration/stm32u5_devices
test suite, core_init.overlay configure msis to use pll-mode.
Since pll-mode is not configured for msik in spi1_msik variant the test
fails since both clocks should support the same configuration regarding
pll mode (an assert in raised in the driver).

Fix this in spi1_msik test variant.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>