arch/x86: Generalize cache manipulation functions (5e4e0298) · Commits · Wenxi XU / zephyr

arch/x86/core/CMakeLists.txt

+1 −0

Original line number	Diff line number	Diff line
		@@ -20,6 +20,7 @@ zephyr_library_sources_ifdef(CONFIG_MULTIBOOT multiboot.c)
		zephyr_library_sources_ifdef(CONFIG_ACPI acpi.c)
		zephyr_library_sources_ifdef(CONFIG_X86_MMU x86_mmu.c)
		zephyr_library_sources_ifdef(CONFIG_USERSPACE userspace.c)
		zephyr_library_sources_ifdef(CONFIG_CACHE_MANAGEMENT cache.c)

		zephyr_library_sources_ifdef(CONFIG_X86_VERY_EARLY_CONSOLE early_serial.c)

arch/x86/core/Kconfig.ia32

+0 −28

Original line number	Diff line number	Diff line
		@@ -144,34 +144,6 @@ config X86_FP_USE_SOFT_FLOAT

		endmenu

		config DCACHE_LINE_SIZE
		default 64 if CPU_ATOM

		config CLFLUSH_INSTRUCTION_SUPPORTED
		bool "CLFLUSH instruction supported"
		depends on !CLFLUSH_DETECT && CACHE_MANAGEMENT
		help
		An implementation of sys_cache_flush() that uses CLFLUSH is made
		available, instead of the one using WBINVD.

		This option should only be enabled if it is known in advance that the
		CPU supports the CLFLUSH instruction. It disables runtime detection of
		CLFLUSH support thereby reducing both memory footprint and boot time.

		config CLFLUSH_DETECT
		bool "Detect support of CLFLUSH instruction at runtime"
		depends on CACHE_MANAGEMENT
		help
		This option should be enabled if it is not known in advance whether the
		CPU supports the CLFLUSH instruction or not.

		The CPU is queried at boot time to determine which of the multiple
		implementations of sys_cache_flush() linked into the image is the
		correct one to use.

		If the CPU's support (or lack thereof) of CLFLUSH is known in advance, then
		disable this option and set CLFLUSH_INSTRUCTION_SUPPORTED as appropriate.

		config X86_DYNAMIC_IRQ_STUBS
		int "Number of dynamic interrupt stubs"
		depends on DYNAMIC_INTERRUPTS

arch/x86/core/ia32/cache.c→arch/x86/core/cache.c

+2 −48

Original line number	Diff line number	Diff line
		/*
		* Copyright (c) 2013-2014 Wind River Systems, Inc.
		* Copyright (c) 2021 Intel Corporation
		*
		* SPDX-License-Identifier: Apache-2.0
		*/
		@@ -16,37 +17,18 @@
		#include <toolchain.h>
		#include <cache.h>
		#include <stdbool.h>
		#include <cache.h>

		/*
		* these functions are defined in cache_s.S
		*/

		extern int z_is_clflush_available(void);
		extern void z_cache_flush_wbinvd(vaddr_t addr, size_t len);
		extern size_t z_cache_line_size_get(void);

		#if defined(CONFIG_DCACHE_LINE_SIZE_DETECT)
		size_t sys_cache_line_size;
		#endif

		#if defined(CONFIG_CLFLUSH_INSTRUCTION_SUPPORTED) \|\| \
		defined(CONFIG_CLFLUSH_DETECT)

		/**
		*
		* @brief Flush cache lines to main memory
		*
		* No alignment is required for either <virt> or <size>, but since
		* sys_cache_flush() iterates on the cache lines, a cache line alignment for
		* both is optimal.
		*
		* The cache line size is specified either via the CONFIG_DCACHE_LINE_SIZE
		* kconfig option or it is detected at runtime.
		* The cache line size is specified via the d-cache-line-size DTS property.
		*
		* @return N/A
		*/

		static void arch_dcache_flush(void *start_addr, size_t size)
		{
		size_t line_size = sys_dcache_line_size_get();
		@@ -76,31 +58,3 @@ int arch_dcache_range(void *addr, size_t size, int op)

		return -ENOTSUP;
		}

		#endif /* CONFIG_CLFLUSH_INSTRUCTION_SUPPORTED \|\| CLFLUSH_DETECT */

		#include <init.h>

		#if defined(CONFIG_DCACHE_LINE_SIZE_DETECT)
		static void init_cache_line_size(void)
		{
		sys_cache_line_size = z_cache_line_size_get();
		}

		size_t arch_cache_line_size_get(void)
		{
		return sys_cache_line_size;
		}
		#endif

		static int init_dcache(const struct device *unused)
		{
		ARG_UNUSED(unused);

		#if defined(CONFIG_DCACHE_LINE_SIZE_DETECT)
		init_cache_line_size();
		#endif
		return 0;
		}

		SYS_INIT(init_dcache, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);

arch/x86/core/ia32.cmake

+0 −2

Original line number	Diff line number	Diff line
		@@ -9,8 +9,6 @@ elseif(CMAKE_C_COMPILER_ID STREQUAL "GNU")
		endif()

		zephyr_library_sources(
		ia32/cache.c
		ia32/cache_s.S
		ia32/crt0.S
		ia32/excstub.S
		ia32/intstub.S

arch/x86/core/ia32/cache_s.S

deleted100644 → 0

+0 −78

Original line number	Diff line number	Diff line
		/*
		* Copyright (c) 2013-2014 Wind River Systems, Inc.
		*
		* SPDX-License-Identifier: Apache-2.0
		*/
		/**
		* @file
		* @brief Cache manipulation
		*
		* This module contains functions for manipulating caches.
		*/

		#include <arch/x86/ia32/asm.h>

		#ifndef CONFIG_CLFLUSH_INSTRUCTION_SUPPORTED

		#if defined(CONFIG_CLFLUSH_DETECT)

		#define CACHE_FLUSH_NAME z_cache_flush_wbinvd
		#define CPUID_CFLSH_BIT (1 << 19)

		GTEXT(z_is_clflush_available)

		SECTION_FUNC(TEXT, z_is_clflush_available)
		pushl %ebx
		movl $1, %eax
		cpuid
		movl %edx, %eax
		andl $CPUID_CFLSH_BIT, %eax
		popl %ebx
		ret

		#else
		#define CACHE_FLUSH_NAME sys_cache_flush
		#endif

		/* externs (internal APIs) */
		GTEXT(CACHE_FLUSH_NAME)

		/**
		*
		* @brief Flush a page to main memory
		*
		* This implementation flushes the whole cache.
		*
		* C signature:
		*
		* void sys_cache_flush (vaddr_t virt, size_t size)
		*
		* Both parameters are ignored in this implementation.
		*
		* @return N/A
		*/

		SECTION_FUNC(TEXT, CACHE_FLUSH_NAME)
		wbinvd
		ret

		#endif /* !CONFIG_CLFLUSH_INSTRUCTION_SUPPORTED */

		#if defined(CONFIG_DCACHE_LINE_SIZE_DETECT)

		#define CPUID_CACHE_LINE_MASK (0xff << 8)

		GTEXT(z_cache_line_size_get)

		SECTION_FUNC(TEXT, z_cache_line_size_get)
		pushl %ebx
		movl $1, %eax
		cpuid
		movl %ebx, %eax
		andl $CPUID_CACHE_LINE_MASK, %eax
		shrl $5,%eax /* shift right 8 to get value, then multiple by 8
		* to get cache line size */
		popl %ebx
		ret

		#endif /* CONFIG_DCACHE_LINE_SIZE_DETECT */

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