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Commit 5dfd3c37 authored by Daniel DeGrasse's avatar Daniel DeGrasse Committed by Carles Cufí
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soc: rt10xx: Set divisor for sys pll (PLL2) PFD0 



Divisor must be set to calculate SD host controller clock frequency in
clock driver.

Fixes #42380

Signed-off-by: default avatarDaniel DeGrasse <daniel.degrasse@nxp.com>
parent 2355fe86
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