dts: riscv: Add sifive,plic-1.0.0 binding and fix riscv,ndev values

Add a new sifive,plic-1.0.0 binding that inherits from the riscv,plic0
binding. The new binding adds a required riscv,ndev property, which
gives the number of external interrupts supported.

Use the new binding for microsemi-miv.dtsi (with a value of 31 for
riscv,ndev, from http://www.actel.com/ipdocs/MiV_RV32IMAF_L1_AHB_HB.pdf

)
and riscv32-fe310.dtsi (which already assigns riscv,ndev).

Also remove a spurious riscv,ndev assignment from
riscv32-litex-vexriscv.dtsi.

Also make edtlib and the old scripts/dts/ scripts replace '.' in
compatible strings with '_' when generating identifiers.

Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>