drivers: clock_control: smartbond: Update clock control driver

This commit should deal with the followings:

1. PLL requires that VDD level be changed to 1V2 and then released
   to 0V9 when it's turned off. Changing the VDD level should be
   done when the regulator driver is available. Otherwise, the VDD
   level will be fixed to 1V2 (reset value).

2. Check if PLL is allowed to be turned off as it might happen that
   USB is enabled which is clocked by PLL.

3. Do not wait for the PLL to lock. This is now performed silently
   when PLL is requested.

4. Before switching to PLL we should check if PLL is already enabled
   as it might happen that PLL node is initially disabled.

Signed-off-by: Ioannis Karachalios <ioannis.karachalios.px@renesas.com>