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Commit 596e44d2 authored by Nathaniel Graff's avatar Nathaniel Graff Committed by Kumar Gala
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soc/riscv32-fe310: Enable DTS gen for SPI 



Add the SPI bus DTS generation to the FE310 and the SiFive Freedom SoC.

Signed-off-by: default avatarNathaniel Graff <nathaniel.graff@sifive.com>
parent 9e2ef8db
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