riscv: fix non-standard assembly of RISC-V

Non-standard `jalr rd, rs` pseudo-instructions are used.
This commit changes them to `ret` for standard return pseudo-instruction
or `jalr rd, rs, 0` for no offset jump register and link.

Fixes #41100.

Signed-off-by: Henry Hsieh <r901042004@yahoo.com.tw>