drivers: regulator: smartbond: Regulator driver update

This commit should deal with the followings:

1. Change regulator's driver priority as it should now
   be used by the clock control driver.
2. Check if the VDD level is permitted to change when PLL
   is the system clock. This is because the PLL requires
   that VDD be 1.2V.

Signed-off-by: Ioannis Karachalios <ioannis.karachalios.px@renesas.com>