soc: riscv: gd32vf103: Fix SYS_CLOCK_HW_CYCLES_PER_SEC to 27000000

As a result of the 11a2107d("riscv: timer: driver revamp") commit,
gd32vf103 no longer works properly.

In the
c9c04e49("soc: riscv: Add initial support for GigaDevice GD32V SoC")
that is the first commit of implementation of this SoC,
set the CPU frequency to CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC,
and riscv_machine_timer divide the clock with the value of
CONFIG_RISCV_MACHINE_TIMER_SYSTEM_CLOCK_DIVIDER.

The CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC should set the timer's clock,
so I fixed to set the config as 27MHz in this PR.  Also, remove the
unnecessary CONFIG_RISCV_MACHINE_TIMER_SYSTEM_CLOCK_DIVIDER setting.

Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>