arch: arm: aarch32:cortex_m: timing.c: cortex M7 may need DWT unlock

On Cortex M7, we need to check the optional presence of
Lock Access Register (LAR) which is indicated in
Lock Status Register (LSR).
When present, a special access token must be written to unlock DWT
registers.

Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>