soc: intel_adsp: Unify vector table generation

This was an abstraction layer without a purpose.  All existing
platforms have the same (LXn core) layout.  When we need to split this
out in the future, the right thing will be to use the values already
provided by the platform core-isa.h and not duplicate them anyway.

Think of this as a first step to an incoming rework of the Zephyr
Xtensa interrupt entry generation, which is long overdue.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>