dts: bindings: watchdog: Add Xilinx Window Watchdog Timer

Xilinx Window Watchdog Timer IP uses window mode.
Window watchdog timer(WWDT) contains closed(first) and open(second)
window with 32 bit width each. Write to the watchdog timer within
predefined window periods of time. This means a period that is not too
soon and a period that is not too late.

The WWDT error interrupts (IRQs) occur when the watchdog timer is not
serviced within the predefined window periods. These IRQs are routed to
the Processing System Manager (PSM) error accumulator module. The PSM is
responsible for managing power and system-level errors, generating a
System on Chip (SoC) reset when a WWDT error occurs. The system reset
event is signaled as a system error for the PSM firmware to handle and a
reset output signal to the MIO/EMIO.

Signed-off-by: Harini T <harini.t@amd.com>