soc: nxp: imx93: m33 early init for GPIO (314686ea) · Commits · Wenxi XU / zephyr

soc/nxp/imx/imx9/imx93/CMakeLists.txt

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Changes for soc/nxp/imx/imx9/imx93/CMakeLists.txt: 1 added line, 0 removed lines.
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		@@ -10,5 +10,6 @@ if(CONFIG_SOC_MIMX9352_A55)
		elseif(CONFIG_SOC_MIMX9352_M33)
		zephyr_include_directories(.)
		zephyr_include_directories(m33)
		zephyr_sources(m33/soc.c)
		set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "")
		endif()

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Changes for soc/nxp/imx/imx9/imx93/Kconfig: 1 added line, 0 removed lines.
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		@@ -21,6 +21,7 @@ config SOC_MIMX9352_M33
		select HAS_MCUX
		select HAS_MCUX_IOMUXC if PINCTRL
		select HAS_MCUX_CACHE
		select SOC_EARLY_INIT_HOOK

		config MCUX_CORE_SUFFIX
		default "_ca55" if SOC_MIMX9352_A55

0 → 100644

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Changes for soc/nxp/imx/imx9/imx93/m33/soc.c: 21 added lines, 0 removed lines.
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		/*
		* Copyright 2025 NXP
		*
		* SPDX-License-Identifier: Apache-2.0
		*/

		#include <zephyr/kernel.h>
		#include <zephyr/device.h>
		#include <zephyr/init.h>
		#include <soc.h>

		#ifdef CONFIG_SOC_EARLY_INIT_HOOK
		void soc_early_init_hook(void)
		{
		/* Configure secure access to pin registers */
		GPIO1->PCNS = 0x0;
		GPIO2->PCNS = 0x0;
		GPIO3->PCNS = 0x0;
		GPIO4->PCNS = 0x0;
		}
		#endif