Skip to content
Commit 3112f856 authored by Daniel Schultz's avatar Daniel Schultz Committed by Benjamin Cabé
Browse files

soc: Add aesc 



Currently, the only available platform is Nitrogen, featuring a
VexRiscv CPU that boots from external SPI flash and runs code from
external HyperRAM.

Signed-off-by: default avatarDaniel Schultz <dnltz@aesc-silicon.de>
parent 14b83d13
Show whitespace changes
Inline Side-by-side
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Please to comment

CRA Git | Maintained and supported by SUSTech CRA and CCSE